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内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
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用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses
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任意数据发生器的源代码-arbitrary data source code generator
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这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
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verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
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伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
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a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
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8*8乘法器设计
伪随机序列发生器
PS2键盘设计
均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
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伪随机数产生器,可以根据输入的控制字产生需要的伪随机数-Pseudo-random number generator
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伪随机比特发生器， VHdL写的伪随机比特发生器-Pseudo-random bit generator, pseudo-random bit generator, VHdL written in pseudo-random bit generator,
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pseudo random bit sequence generator
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伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
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巴克码发生器的VHDL程序，巴克码主要用于通信系统中的帧同步，便于与随机的数字详细相区别，易于识别。-Barker Code Generator VHDL program, Barker Code is mainly used for frame synchronization in communication systems, and the random number to facilitate more differentiated and easy identification.
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一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
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上传的几个VHDL程序：分别是各种功能计数器；使用列举类型的状态机，四D触发器，通用寄存器，伪随机比特发生器，简单的状态机。-Upload several VHDL program: are the various functions of the counter using the enumerated type state machine, four D flip-flop, the general-purpose registers, pseudo-random bit generato
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伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）--Design of VHDL algorithm for pseudo random sequence generator is a pseudorandom sequence generator, using the generating polynomial 1+X^3+X^7. RESET has a cli
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伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
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伪随机序列发生器，即M序列发生器，VHDL语言完成，已仿真通过。-Pseudo-random sequence generator, VHDL language completed, through simulation.
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Linear Feedback Shift Register (LFSR)/Random number generator
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random number generator - 16bit
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